1. Field of the Invention
The present invention relates to I/O circuitry for integrated circuits.
2. State of the Art
Complex integrated circuits are often I/O-limited, meaning that the die size is increased beyond what would otherwise be required in order to accommodate the required number of I/Os. For integrated circuits generally, and especially I/O-limited integrated circuits, design of the I/O portion of the integrated circuit is often laborious and time-consuming. At the same time, short product design cycles call for short integrated circuit design cycles. Reducing design time and labor for integrated circuits, including complex, I/O limited integrated circuits, requires new approaches.
FIG. 1 shows a top view of the layout of a portion 300 of I/O circuitry of an example IC die, according to the prior art. I/O circuitry 300 could run along any edge of the periphery of an IC die. The I/O circuitry 300 uses two concentric rows of bond pads, i.e., inner pad row 1 and outer pad row 2. The pad placements along the peripheral edge are offset between the two rows. During the wire bonding process, all pads along the outer row 2 are typically wire bonded before any bond pads on inner row 1 are wire bonded (or vice versa). This arrangement enables I/O pads to be packed more densely without exceeding the capabilities (minimum pad pitch) of wire bonding equipment.
Bond pads in FIG. 1 include signal bond pads (SIG) 201 and power/ground bond pads. Power/ground bond pads in turn include power bond pads (VCC CORE) 204 for a core logic portion of the integrated circuit, ground bond pads (VSS CORE) 205 for the core logic portion of the integrated circuit, power bond pads (VCC IO) 202 for the I/O portion of the integrated circuit, and ground bond pads (VSS 10) 203 for the 10 portion of the integrated circuit. Each of the foregoing pads is coupled to a corresponding one of I/O cells 130, including differentiated signal I/O cells (SIG 10) 211, core logic power 110 cells (VCC CORE) 214, core logic ground cells (VSS CORE) 215, I/O power cells (VCC IO) 212, and I/O ground cells (VSS 10) 213. A primary function of the four power/ground cells 130 is to provide electrostatic discharge (ESD) protection to the associated power/ground pads and supply power and ground to a group of I/O cells (SIG 10) 211.
Each of the cells 130 occupies an I/O slot, the I/O slots being spaced apart according to a specified pitch. For a complex integrated circuit, roughly 30% of the I/O pads will typically be power/ground pads, and a corresponding proportion of the cells 130 will be power/ground cells.